So I started looking at other options. Si570 looked nice, but here the lower limit was the problem: 10 MHz. Even with divide by 4, that knocks out 160 meters, a band I am very interested in lately, and that seems to sound especially good in a direct conversion receiver.
Once again, the controversial Si5351 was calling my name. It would go down to 8 kHz and up to 160 Mhz. Woo Hoo! If I could build a divide by 2 IQ VFO, I could cover 160-6 meters.
Here is the basic idea. From:
http://www.markimicrowave.com/blog/2015/04/top-7-ways-to-create-a-quadrature-90-phase-shift/
With lots of hardware help from Todd VE7BPO, and software help from Tom AK2B (wizards both), I got my Si5351 divide by 2 circuit working today. You can see the resulting I and Q in the picture at the top. But I am discovering that there may have been wisdom behind those divide by 4 circuits. My opposite sideband suppression isn't as good with this /2 scheme as it was with the AD9850 divide by 4. I'm still trying to figure out why. I may have to go back to divide by 4. Stay tuned.
I'm wondering if there's enough delay in the inverter to throw the phase out? try inverting the 0-deg (top) output and see.
ReplyDeleteThe problem you have with this circuit is that the added inverter delay adds a small phase shift in the signal going to the second flip-flop. This causes the signals phase to be slightly different than the 90 degrees you are looking for. To use the circuit the way you want you need to feed the 2 flip-flops with a signal that is exactly 180 degrees out of phase. One way to do that is to use two exclusive or gates. One input on each tied together. The other on one pulled up, and on the second one tied to ground. Since the signals are both going through a gate there is no delay in one signal. This should give two signals that are exactly 180 degrees out of phase triggering the flip-flops.
ReplyDelete73
DuWayne
KV4QB
The gate delay in the inverter side may be enough to delay the flip/flop by a significant amount. Is the sideband suppression better on low frequencies than on high frequencies?
ReplyDeleteAssume the inverter has zero delay. Assume the 2f input has 50% mark space ratio. The circuit will work. If the mark space ratio drifts, so will the delay between the two outputs of the d flip flops. A 50% mark space ratio is needed at all frequencies. This can be achieved by putting the input via a d flip flop, but this brings you back to divide by 4 :-)
ReplyDelete73 Joe vk3bki
DuWayne has it right: both F/Fs driven at 2f, each through an identical gate but exactly antiphased. My earlier post might have made an improvement, but perhaps not fully.
DeleteYes, 74HC86 as buffer/phase splitter, but the AD9850 board has two square wave outputs, so try that, I shall on next version of phasing rx. good luck
ReplyDelete73 de Stephen VK2BLQ
In August 1973, Shubert had an article in "Ham Radio" about a direct conversion phasing receiver, using MC1496's and an ECL dual flip flop for the RF phasing. His circuit divided by two, I think, but they were cross coupled in some way, to limit delay. The ECL helped too, really fast compared to TTL of the time. But even then, it stopped being useful around about 15MHz.
ReplyDeleteHe explained it, and later some more, in letters and about 1975, when he had a followup article, a phasing transmitter.
I can't remember the circuit, and the magazine isn't handy. Maybe he used J-K flip flops and/or the inverter was in series with both.
Some of the books show a method that only divides by two, but I can't find any such circuits now. Maybe "recent" ARRL Handbooks, after phasing made a comeback.
That gate is obviously going to add delay, the more so the higher the frequency. I don't think I've ever seen that circuit seriously proposed.
Michael
Hello,
ReplyDeleteThe Si570 does not stonewall at 10MHz (or at 160MHz), it's just the recommended range. Mine works flawlessly from below 4MHz to over 220MHz, covering 1Mhz to 55MHz in a divide-by-4 configuration, and most of the people using them in SDR transceivers have the same results. The Genesis SDR transceivers (G11 or G59) are using Si570 and advertising 160m-6m coverage without even pretesting the clock generators. It also has better phase noise than the Si5351 and MUCH better phase noise and spurs than the AD985x series. Look here, RX test in the MW broadcast band: https://www.youtube.com/watch?v=Y3e5atQ4bQ4
Can't the AD9850 output 2 sinewaves at 90° phase offset?
ReplyDeleteI believe you need two AD9850's to do that but indeed it can be done.
DeleteThe AD9850 would not give the frequency range Bill is looking for. The square wave outputs are complimentary, 180 degrees. But, on the 9850 modules there is a small pot that is used to adjust the duty cycle of the square wave output. I think that if it is not exactly at 50% you will probably get a phase difference other than 90 degrees from the flip-flops.
ReplyDeleteHi Bill,
ReplyDeleteCheck out the schematic on the page at this site:
http://www.wb5rvz.org/ensemble_rx_iii/04_div
It is the divide by four circuit used in the softrocks. Both divides are clocked at the same time and it doesn't require the inverter. You can use the divide by four with the SI5351.
73 - W8NFT
This comment has been removed by the author.
ReplyDeleteBill, I have been following this project with interest as it is so appealing. I have a lot to learn about such techniques.
ReplyDeleteI thought naively that you could just generate the quadrature output directly from 2 of the outputs of the Si chip. I did find this link that refers to doing that. Don't know if it will help or not with the sideband suppression. They claim it was OK at 20 MHz. http://community.silabs.com/t5/Timing/Difficulty-setting-phase-on-Si5351/td-p/141099
I also read that for a multiband receiver that you may require a filter for each band to make sure that receive signals on odd harmonics of the LO don't get detected. Is that right?
I will be following for more news.
73
David GM4JJJ
Another thought: does the output of your 2f chip allow fine control of duty cycle? An adjustment of that could compensate for the inverter delay.
ReplyDeleteFor static divide by 2, you might want to try generating the input to the flipflops with two XOR gates, to avoid introducing unequal phase delay going into the flipflops. This, as you have already seen by adding an inverter in the signal path of only one of the flipflops creates a phase difference. Configure XOR gate 1 as one pin to VCC and one to Clk which will give you inverted Clk out, and XOR gate 2 one pin to Clk and one to Gnd which will give you Clk out. That should equalize the phase delay going into the flipflops.
ReplyDeleteThe divide by 4 you have implemented is a Johnson Counter btw, a ring counter with an inversion (ie Q inverse back to first D).
ReplyDeleteBill
ReplyDeleteTime marches on. Look what's now available from Mouser (as in, in stock - $18). Si570, 10 mhz to 810 mhz. You'd need high speed dividers.
Also, for those lower frequencies, divide by 10. Somebody did a board for that recently to get down to Lowfer band but my memory is failing at the moment.
Ed, N5EM
I lost the URL - http://tinyurl.com/htct8fv
ReplyDeleteEd