https://newsroom.ibm.com/2026-06-25-ibm-debuts-worlds-first-sub-1-nanometer-chip-technology
FCC Amateur Radio Exam Question: Draw the schematic for the new IBM sub-1nm chip, showing how it will be used in FT-8 operations.
Mike WN2A suggested I ask AI about a schematic. Here is what Gemini said:
To put that number into perspective, if we were to draw a schematic where each transistor was just a tiny 1-inch symbol on a piece of paper, the blueprint would be so massive it would easily cover the entire landmass of the United States.
Modern sub-nanometer chips—like IBM's cutting-edge nanosheet architectures—are far too complex for human hands to map out line-by-line. Instead, engineers use advanced software to design chips hierarchically. Here is how that massive sea of 100 billion transistors is actually organized under the hood:
1. The Building Block: The Gate-All-Around (GAA) Nanosheet
At the microscopic level, these chips no longer use the older FinFET (fin-shaped) transistors. Instead, they use nanosheets, where the channels are stacked vertically like a three-story sandwich. The gate wraps entirely around all four sides of each horizontal sheet, providing maximum electrical control and drastically reducing current leakage.
2. Standard Cells (The Functional Logic)
Instead of wiring 100 billion separate components, computer scientists group transistors into "Standard Cells." These are pre-designed functional blocks like:
Logic Gates: AND, OR, NAND, and NOR gates (requiring anywhere from 2 to 8 transistors each).
Flip-Flops: Memory cells that store a single bit of data (requiring about 20 to 30 transistors).
3. The Macroscopic Layout (Blocks and Cores)
Billions of those standard cells are then combined into macroscopic structural blocks that look less like a traditional schematic and more like a highly organized city map. If we were to draw a high-level schematic of the chip, it would look like a block diagram featuring:
Processor Cores: The massive processing engines packed with arithmetic logic units (ALUs).
Cache Memory (SRAM): Vast grids of 6-transistor memory cells stacked tightly together to hold data right next to the execution units.
Interconnect Matrix: A vertical 3D skyscraper of up to 15 layers of microscopic copper wiring running above the transistors to route data and power across the chip.
If you are working on a homebrew electronics project and want to map out a circuit diagram for an RF amplifier, a QRP radio transceiver, or a simple analog filter, I can absolutely help you draw or troubleshoot those schematics! But for 100 billion nanosheets, we have to leave the drafting to the silicon foundries' supercomputers.
